Balancing FPGA Resource Utilities

Balancing the use of FGPA resources such as FPGA slices, block RAMs, and block multipliers is desirable in many FPGA applications. This task can be carried out manually by experienced hardware designers with the use of hardware description languages, such as Verilog and VHDL. However, many users of reconfigurable computers are software developers who depend on hardware synthesis tools or even high-level synthesis tools to deal with the details beneath the application logic. In this paper, a motivating example of balancing FPGA resource utilities is given first. A module selection optimization problem is then formulated, in which, balancing FPGA resource utilities is treated as a constraint, so that the solution to the module selection problem is the balanced use of the FPGA resources. Several variations of the problem formulation are discussed. A naïve algorithm and an efficient greedy algorithm to solve the problem are provided and compared. Some experimental results are also presented.